发明名称 ASYNCHRONOUS LOGIC CIRCUIT
摘要 <p>A transmission source register stores data in the memory element thereof and transmits a data storage request. In response to the data storage request, a transmission destination register stores the data, which is stored in the transmission source register, in the memory element thereof and transmits a data storage completion notification. In an asynchronous logic circuit, a possible congestion duration measurement module counts when the data storage completion notification is not transmitted from the transmission destination register in response to the data storage request from the transmission source register and outputs the time corresponding to the counted value as the possible congestion duration. A handshake switch module outputs the data storage request from the transmission source register to the transmission destination register that is a first transfer destination when the possible congestion duration is less than an established time and outputs the data storage request from the transmission source register to a second transfer destination when the possible congestion duration is an established time or greater. Thus, communication capacity can be effectively utilized in the asynchronous logic circuit.</p>
申请公布号 WO2010082575(A1) 申请公布日期 2010.07.22
申请号 WO2010JP50259 申请日期 2010.01.13
申请人 NEC CORPORATION;TANAKA KATSUNORI 发明人 TANAKA KATSUNORI
分类号 H03K19/0175 主分类号 H03K19/0175
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