| 摘要 |
Techniques for converting an accumulated phase of a signal into a digital value in a digital phase-locked loop (DPLL). In an exemplary embodiment, a signal is coupled to a divide-by-N module that divides the frequency of the signal down by a divider ratio N. The divided signal is input to a delta phase-to-digital converter, which measures the phase difference between a rising edge of the divided signal and a rising edge of a reference signal. The accumulated divider ratios and the measured phase differences are combined to give an accumulated digital phase. Further techniques for varying the divider ratio N using a sigma-to-delta modulator are disclosed.
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