发明名称 |
MECHANISM FOR INCREASING THE EFFECTIVE CAPACITY OF THE WORKING REGISTER FILE |
摘要 |
A computer processor pipeline has both an architectural register file and a working register file. The lifetime of an entry in the working register file is determined by a predetermined number of instructions passing through a specified stage in the pipeline after the location in the working register file is allocated for an instruction. The size of the working register file is selected based upon performance characteristics. A working register file creditor indicator is coupled to the front end pipeline portion and to the back end pipeline portion. The working register file credit indicator is monitored to prevent a working register file overflow. When the a location in the architectural register file is read early, the location is monitored to determine whether the location is written to prior to issuance of the instruction associated with the early read.
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申请公布号 |
US2010180103(A1) |
申请公布日期 |
2010.07.15 |
申请号 |
US20090354206 |
申请日期 |
2009.01.15 |
申请人 |
CHAUDHRY SHAILENDER;CAPRIOLI PAUL;TREMBLAY MARC |
发明人 |
CHAUDHRY SHAILENDER;CAPRIOLI PAUL;TREMBLAY MARC |
分类号 |
G06F9/38;G06F9/312 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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