| 摘要 |
A gate driver for driving k pixel rows of a liquid crystal display panel, wherein k is a natural number greater than 1. The gate driver includes a shift register circuit and an output logic circuit. The shift register circuit outputs an ith first shift signal and a jth second shift signal in a scan period according to a multiple-level startup signal. The ith first shift signal and the jth second shift signal correspond to the first and second pixel rows, respectively, wherein i and j are natural numbers smaller than or equal to k. The output logic circuit is controlled by a multiple-level output enable signal to provide the ith first and jth second shift signals to drive the first and second pixel rows in a data-input sub-period and a black-insertion sub-period of the scan period, respectively. The data-input sub-period and the black-insertion sub-period are non-overlapped.
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