| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To attain, in a simple circuit configuration, a clock generating circuit capable of shortening the time required for lock, even if a reference clock at any frequency within a wideband frequency range is received. <P>SOLUTION: The clock generating circuit includes a delay unit 11 for generating a first delay clock, by making a reference clock through a first number of voltage controlled delay elements 12-1 to 12-N delayed and for generating a second delay clock, by delaying the reference clock through a second number of voltage controlled delay elements 12-1 to 12-K; a phase comparator 21 for comparing a phase of the reference clock with that of the first delay clock; a charge pump 22 for outputting a delay control current; a delay control unit 23; a determination unit 13a for comparing the phase of the reference clock with that of the second delay clock and determine the phase difference between the reference clock and the first delay clock; and a charge control unit 13b for performing a control, such that when the phase difference is greater than the threshold, the delay control current becomes a first value; and when the phase difference is smaller than or equal to the threshold, the delay control current becomes a second value which is smaller than the first value. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
