| 摘要 |
An improved FPGA having a direct interconnect structure to provide selective data routing without stressing the general-purpose routing resources and to enable high rate of data exchange within the FPGA. At least two IP cores are connected to each other through the direct interconnect structure to enable simultaneous data interaction among the ports of the IP cores and to provide configurable bus width routing between the IP cores, and a plurality of logic blocks connected to the IP cores through the direct interconnect structure to enable simultaneous data routing among the IP cores and the plurality of logic blocks.
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