发明名称 CHIP ON LEAD WITH SMALL POWER PAD DESIGN
摘要 Embodiments of a semiconductor device and method provide a quad flat no-lead semiconductor package which can have an arrangement of both chip-on-lead (COL) style leads and a die pad for supporting a die, and can also provide non-COL leads, both COL leads and a leadframe power pad, COL leads which have varying lengths to reduce stress resulting from thermal mismatch between a semiconductor die and leads, and a die pad with a curved, meandering edge to reduce stress resulting from thermal mismatch between the semiconductor die and the die pad.
申请公布号 US2010171201(A1) 申请公布日期 2010.07.08
申请号 US20090349197 申请日期 2009.01.06
申请人 发明人 WYANT M. TODD;HOLLOWAY JEFFREY G.;COYLE ANTHONY L.
分类号 H01L23/52;H01R43/00 主分类号 H01L23/52
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