Method and Apparatus to Suppress Fringing Field Interference of Charge Trapping NAND Memory

摘要

With advanced lithographic nodes featuring a half-pitch of 30 nm or less, charge trapping NAND memory has neighboring cells sufficiently close together that fringing fields from a neighboring pass gate interferes with the threshold voltage. The interference results from fringing fields that occupy the gaps that separate the neighboring charge storage structures. The fringing electric fields are suppressed, by the insulating structures having a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide, from entering the neighboring charge storage structures. In some embodiments, the insulating structures suppress the fringing electric fields from entering a channel region. This suppresses the short channel effects despite the small dimensions of the devices.