发明名称 |
Output Buffer Circuit with Enhanced Slew Rate |
摘要 |
An output buffer circuit with enhanced slew rate is disclosed. A first and a second slew-rate enhancing transistor are configured to enhance the slew rate of the source transistor and the sink transistor of an output stage. A first control circuit and a second control circuit turn off the first and the second slew-rate enhancing transistors during the static state, and turn on the first and the second slew-rate enhancing transistors during the transition.
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申请公布号 |
US2010171727(A1) |
申请公布日期 |
2010.07.08 |
申请号 |
US20090349432 |
申请日期 |
2009.01.06 |
申请人 |
CHEN YI-JAN EMRY;LIU PANG-JUNG;JIANG JYUN-PING;WU TSUNG-YU |
发明人 |
CHEN YI-JAN EMRY;LIU PANG-JUNG;JIANG JYUN-PING;WU TSUNG-YU |
分类号 |
G06F3/038 |
主分类号 |
G06F3/038 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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