| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an image processing apparatus that executes error diffusion processing of a pixel value with a smaller amount of hardware resources compared with a case when not having this configuration. <P>SOLUTION: A shift arithmetic unit included in an error addition circuit 32 subjects an input quantization error to a shift arithmetic operation so as to set it to a predetermined ratio and outputs it to an adder. The adder adds a pixel value P<SB>x, Y</SB>, in which the quantization error is cumulatively added by error diffusion processing, to the quantization error, subjected to the shift arithmetic operation, and outputs it to a shift register. The shift register outputs the input value to an error addition circuit 32 serially connected in the main-scanning direction. Eight error diffusion processing circuits 30 are serially connected in the main-scanning direction. Each error diffusion processing circuit 30 is input with an output value of the pre-stage error diffusion processing circuit 30 and the corresponding pixel value P<SB>X, Y</SB>at the same timing by a delay circuit 40. An output value of the last-stage error diffusion processing circuit 30 is stored in an error buffer circuit 38 and output to the first-stage error diffusion processing circuit 30 when the next parallel processing is executed. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
