| 摘要 |
<p>PURPOSE: A method for designing a test chip is provided to reduce the waste that occurs during a first state for design by removing a risk element in advance. CONSTITUTION: The number of cell chains and power pads which are designed for a test chip is designed(S102), and the power of the test chip in which the power pads are designed is measured(S103). The size of the test chip is determined by using the number of the cell chains and the power pads(S104). The arrangement and wiring for physical layout and logic configuration are performed according to the determined size of the test chip(S105).</p> |
