| 摘要 |
<p>PURPOSE: A structure and a method for improving the connection of solder bumps in a semiconductor device are provided to prevent the generation of cracks or delaminations in a lower back-end-of-line vias, metal interconnects, pads, and wires. CONSTITUTION: An upper wiring layer is formed in a dielectric level. One or more dielectric layers(20, 22) are deposited on the upper wiring layer. A plurality of separated vias is formed in the dielectric layers. A ball-limiting metallurgy or an under-bump metallurgy is deposited in the separated vias. Solder bumps(28) are formed on separated metal islands. A metal layer(40) is formed between the solder bump and the separated metal islands.</p> |
