| 摘要 |
According to one embodiment, a memory control apparatus includes a generator configured to delay a clock signal having a rise and a fall that appear in a constant cycle and to generate a plurality of delay clock signals having delay times different from each other; an extractor configured to extract, from a data signal including reference data, data of a portion corresponding to the rise or fall of each delay clock signal generated; a first determiner configured to determine whether each data extracted coincides with the reference data; and a second determiner configured to determine, from the delay times of the delay clock signals corresponding to the data that have been determined to coincide, a range of the delay time with respect to the rise of the clock signal and a range of the delay time with respect to the fall of the clock signal.
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