| 摘要 |
PURPOSE: A DLL(Delay Locked Loop) circuit is provided to accurately perform a delay locked operation by compensating for the timing variation of a clock due to a duty cycle compensation operation. CONSTITUTION: A clock input buffer(10) generates a reference clock by buffering an external clock. The clock input buffer corrects a duty cycle of a reference clock in response to a duty cycle control signal. A timing compensating unit(20) generates a compensation reference clock by recompensing for the toggle timing of the changed reference clock in response to the timing control signal in the duty cycle correction operation. A duty cycle control unit(30) generates the duty cycle control signal and the timing control signal by sensing the duty cycle of the reference clock. The clock input buffer comprises a buffering unit to generate a reference clock and a duty cycle control unit to control the duty cycle of the reference clock.
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