CIRCUIT ARRANGEMENT FOR FILTERING UNWANTED SIGNALS FROM A CLOCK SIGNAL, PROCESSING SYSTEM AND METHOD OF FILTERING UNWANTED SIGNALS FROM A CLOCK SIGNAL

摘要

A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement.