| 摘要 |
A semiconductor memory apparatus includes a data bus inversion (DBI) section configured to receive a plurality of input data and decide whether to invert or output, without an inversion, the plurality of input data depending upon logic levels of the plurality of data, and further configured to generate a plurality of inversion data based on the decision; and a data output section configured to receive the plurality of inversion data, invert or output, without an inversion the plurality of inversion data in response to a mode signal, and generate a plurality of output data.
|
