发明名称 WRITE CIRCUITRY FOR HIERARCHICAL MEMORY ARCHITECTURE
摘要 A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.
申请公布号 US2010157699(A1) 申请公布日期 2010.06.24
申请号 US20090641102 申请日期 2009.12.17
申请人 STMICROELECTRONICS PVT. LTD. 发明人 GUPTA SIDDHARTH;JAIN NITIN;MISHRA ANAND
分类号 G11C11/416;G11C7/10;G11C8/00;G11C8/18 主分类号 G11C11/416
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