| 摘要 |
A shift register is disclosed. The shift register includes a plurality of stages for sequentially outputting scan pulses, wherein each of the stages includes a scan pulse output unit controlled according to voltage states of a set node and reset node for outputting a corresponding one of the scan pulses and supplying the corresponding scan pulse to a corresponding gate line, a carry pulse output unit controlled according to the voltage states of the set node and reset node for outputting a carry pulse and supplying it to an upstream one of the stages and a downstream one of the stages, a first node controller for controlling the voltage states of the set node and reset node according to a carry pulse from the upstream stage, a carry pulse from the downstream stage and a first control signal externally supplied thereto, an all-drive signal output unit controlled according to voltage states of a control node and reset control node for outputting an all-drive signal and supplying it to the corresponding gate line, and a second node controller for controlling the voltage states of the control node and reset control node according to the voltage state of the set node, the voltage state of the reset node, and a start pulse and second control signal externally supplied thereto.
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