发明名称 |
Acceleration of header and data error checking via simultaneous execution of multi-level protocol algorithms |
摘要 |
An error detection system and methodology where the undesirable consequence of encapsulation (additional latency or delay) for virtualization applications such as i-PCI or iSCSI is minimized for the vast majority of data transactions. Cyclic Redundancy Checks (CRCs) and checksums are executed simultaneously in parallel, immediately on reception of a data packet regardless of the relative processing order in relation to the OSI model.
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申请公布号 |
US2010162066(A1) |
申请公布日期 |
2010.06.24 |
申请号 |
US20090653829 |
申请日期 |
2009.12.18 |
申请人 |
PAPIRLA VEERA;DANIEL DAVID A |
发明人 |
PAPIRLA VEERA;DANIEL DAVID A. |
分类号 |
H03M13/09;G06F11/07;G06F11/10 |
主分类号 |
H03M13/09 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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