| 摘要 |
FIELD: physics, communications. ^ SUBSTANCE: invention is aimed at a method and device for low-density parity-check code (LDPC) decoding. The LDPC decoder is made with a parallelism level which is less complete than parallelism of the code structure used for controlling the decoding process. Each instruction regarding the simple control code used for describing the code structure can be stored and executed several times in order to decode a code word. Different values of the length of the code word are supported using one set of code control instructions but the code is realised a different number of times depending on the length of the code word. The decoder can switch between decoding code words of different length without need for altering stored code description information by simply changing the code extension coefficient which indicates the length of the code word and is used for controlling the decoding process. When decoding code words which are shorter than the maximum supported length of the code word, certain cells of memory blocks can remain unused. ^ EFFECT: higher transmission capacity due to provision for structured parallelism. ^ 18 cl, 8 dwg |
