发明名称 PARALLEL PLANE MEMORY AND PROCESSOR COUPLING IN A 3-D MICRO-ARCHITECTURAL SYSTEM
摘要 <p>An IC device (10) is constructed in a manner that allows for the memory (12), (13) and processor elements (11), (14) to be positioned one above the other on parallel planes of a 3-D structure. Interconnections (31), (32), (33) between the memory (s) and the processor (s) are accomplished by using through substrate stacking (TSS) techniques. This arrangement provides the processor with direct access to the memory by reducing the distance between the memory and the processor.</p>
申请公布号 WO2010068785(A1) 申请公布日期 2010.06.17
申请号 WO2009US67544 申请日期 2009.12.10
申请人 QUALCOMM INCORPORATED;TOMS, THOMAS R. 发明人 TOMS, THOMAS R.
分类号 H01L25/18;H01L25/065 主分类号 H01L25/18
代理机构 代理人
主权项
地址