发明名称 |
SERIAL TO PARALLEL CONVERTING CIRCUIT |
摘要 |
PURPOSE: A serial-parallel converting circuit is provided to prevent malfunction due to a timing margin shortage by controlling the resonance variation and the timing variation due to an external environment. CONSTITUTION: A first register block(140) comprises a plurality of first registers for extracting parallel data to serial data in response to a first latching signal. A delay block(150) comprises a plurality of delaying elements which delays the parallel data outputted from a corresponding first register among the first registers by a predetermined time. A second register block(160) comprises a plurality of second registers which, in response to a second latching signal, latches the parallel data outputted from a corresponding delaying element among the delaying elements. A third register block(170) comprises a plurality of third registers for latching the parallel data outputted from a corresponding second register among the second registers in response to the first latching signal.
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申请公布号 |
KR20100062651(A) |
申请公布日期 |
2010.06.10 |
申请号 |
KR20080121376 |
申请日期 |
2008.12.02 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
BAEK, SEUNG HOON;LEE, JUNG BONG |
分类号 |
H03M9/00;G06F13/00 |
主分类号 |
H03M9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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