发明名称 FREQUENCY CALIBRATION LOOP
摘要 PURPOSE: A frequency adjustment loop is provided to form a lock state of the frequency adjustment loop within fast time by moving an output frequency of an oscillator to wanting frequency band. CONSTITUTION: An oscillator(140) controls an output frequency according to inputted control bit. A programmable divider(150) divides the output frequency of the oscillator according to varied dividing ratio. A counter unit(110) is inputted an output signal of the programmable divider and a reference frequency. The counter unit measures a clock number of the output signal of the divider in one period of the reference frequency. A frequency detector(120) outputs the value tacking out from the clock number outputted from the counter unit in a standard comparison value to a control bit of the oscillator. The programmable divider decides the divide ratio about the output signal of the oscillator by receiving a feedback the clock number outputted from the counter unit.
申请公布号 KR20100062806(A) 申请公布日期 2010.06.10
申请号 KR20090023897 申请日期 2009.03.20
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 MIN, BYUNG HUN;LEE, JA YOL;KIM, SEONG DO;KIM, CHEON SOO;YU, HYUN KYU
分类号 H03L7/16;H03L7/00 主分类号 H03L7/16
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