摘要 |
Driving a 1-transistor DRAM composed of an NMOS on top of a SOI layer such that the 1-transistor DRAM has a corresponding parasitic bipolar transistor component includes precharging, shifting, and deactivating steps. Implementing these steps can result in enhancing the performance of reading, writing and storing binary logic information within the 1-transistor DRAM memory device.
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