发明名称 High selectivity etching process for metal gate N/P patterning
摘要 A method for fabricating a integrated circuit with improved performance is disclosed. The method comprises providing a substrate; forming a hard mask layer over the substrate; forming protected portions and unprotected portions of the hard mask layer; performing a first etching process, a second etching process, and a third etching process on the unprotected portions of the hard mask layer, wherein the first etching process partially removes the unprotected portions of the hard mask layer, the second etching process treats the unprotected portions of the hard mask layer, and the third etching process removes the remaining unprotected portions of the hard mask layer; and performing a fourth etching process to remove the protected portions of the hard mask layer.
申请公布号 US7732344(B1) 申请公布日期 2010.06.08
申请号 US20090478922 申请日期 2009.06.05
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 TSAI FANG WEN;YEH MATT;WANG MING-JUN;LIN SHUN WU;CHEN CHI-CHUN;WEI ZIN-CHANG;CHERN CHYI-SHYUAN
分类号 H01L21/302 主分类号 H01L21/302
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