发明名称 |
System and method for packet transmission from fragmented buffer |
摘要 |
The present invention is directed to methods and systems for implementing a DMA scheduling mechanism and a DMA system for transmission from fragmented buffers. According to an aspect of the present invention, a processor controls several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. According to another aspect of the present invention, a system for handling transmission of network packets which are assembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor.
|
申请公布号 |
US7733878(B2) |
申请公布日期 |
2010.06.08 |
申请号 |
US20030614109 |
申请日期 |
2003.07.08 |
申请人 |
BROOKTREE BROADBAND HOLDINGS, INC. |
发明人 |
KNIGHT BRIAN;MILWAY DAVID;HOLLAND CHRIS |
分类号 |
H04L12/28;G06F13/28 |
主分类号 |
H04L12/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|