发明名称 LAYOUT VERIFICATION DEVICE, LAYOUT DEVICE, LAYOUT VERIFICATION METHOD, LAYOUT VALIDATION PROGRAM, AND WIRING FORMATION METHOD
摘要 <p><P>PROBLEM TO BE SOLVED: To correct layout wiring data while fixing the position of a terminal even when using a method for detecting a defective section based on a simulation result. <P>SOLUTION: A layout verification device includes: a verification means for acquiring mask data showing a mask pattern to be plotted on a mask based on layout wiring data showing the positions of a primitive cell group and connection wiring connected to the primitive cell group, and for verifying the position of the mask pattern based on the mask data, and for detecting an error section; and a correction hint creation means for generating correction hint information based on the error section, and for notifying a layout wiring means for correcting the layout wiring data about the correction hint information. The correction hint creation means obtains terminal information showing the position of a terminal group included in the primitive cell group, and for generating the correction hint information so that the layout wiring means does not change the position of the terminal, based on the terminal information. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2010117851(A) 申请公布日期 2010.05.27
申请号 JP20080290083 申请日期 2008.11.12
申请人 NEC ELECTRONICS CORP 发明人 HAMAMOTO TAKESHI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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