发明名称 METHOD FOR FABRICATING SEMICONDUCTOR DEIVCE WITH VERTICAL GATE
摘要 <p>PURPOSE: A method for fabricating a semiconductor device including a vertical gate is provided to prevent the generation of voids during a conductive deposition process by forming a conductive layer which functions as the vertical gate and a word-line before active pillars are formed. CONSTITUTION: A hard mask layer, a conductive layer and an insulation layer are successively stacked to form a stacked structure. The hard mask layer is the upper region of the stacked structure. The conductive layer and the insulation layer are the lower region of the stacked structure. The stacked structure, which includes a pillar region, is formed on the upper side of a substrate. The line wide in the upper side of the pillar region is wider than the line width in the lower side of the pillar region. A gate insulation layer(28) is formed on the lateral side of the pillar region. An active pillar(29) is formed to gap-fill the pillar region. The conductive layer is selectively etched to form a vertical gate.</p>
申请公布号 KR20100053861(A) 申请公布日期 2010.05.24
申请号 KR20080112689 申请日期 2008.11.13
申请人 HYNIX SEMICONDUCTOR INC. 发明人 JUNG, YOUNG KYUN
分类号 H01L29/78;H01L21/336 主分类号 H01L29/78
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