| 摘要 |
<p>A pixel signal picked up and obtained by a solid state image picking-up element is so configured that the output of n bits synchronized with an output clock and that of n integral multiple bits are available for selection. In order to carry out these operations, a clock conversion unit (26), a sort unit (32), a first selector (31), a second selector (27) and an output mode control unit are provided. The sort unit (32) alternatively sorts each of bit data of the pixel signal picked up and obtained by the solid state picking-up element into at least two series of bit data in synchronization with a clock converted by the clock conversion unit (26). The first selector (31) selects an output of the bit data sorted by the sort unit (32) and that of non-sorted bit data. The second selector (27) selects an output of the frequency clock converted by the clock conversion unit (26) and that of a non-converted frequency clock.</p> |
