| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To solve the following problem: in data transfer by an asynchronous clock, due to a metastable countermeasure, latency is increased as compared to a synchronous design, so that data transfer performance deteriorates. <P>SOLUTION: A computer system includes: a processor 101; a submodule 103 connected to the processor 101; an external access monitoring part 204 for monitoring data transfer between the processor 101 and the submodule 103; and a synchronous-asynchronous control part 207 for controlling whether to transit a processor clock such that the processor clock is synchronized with a submodule clock or that it is not synchronized, according to a result of the monitoring. Specifically, according to frequency with which the processor 101 accesses the submodule 103, the processor clock is transited such that the processor clock is synchronized with the submodule clock when the access frequency is high, and the processor clock is transited such that the processor clock is not synchronized with the submodule clock when the access frequency is low. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
