发明名称 |
MULTITHREADED PROCESSOR WITH MULTIPLE CONCURRENT PIPELINES PER THREAD |
摘要 |
A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.
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申请公布号 |
US2010122068(A1) |
申请公布日期 |
2010.05.13 |
申请号 |
US20090579867 |
申请日期 |
2009.10.15 |
申请人 |
HOKENEK ERDEM;MOUDGILL MAYAN;SCHULTE MICHAEL J;GLOSSNER C JOHN |
发明人 |
HOKENEK ERDEM;MOUDGILL MAYAN;SCHULTE MICHAEL J.;GLOSSNER C. JOHN |
分类号 |
G06F9/30;G06F1/04;G06F9/46;G06F15/00 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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