发明名称 Layout verification apparatus, layout apparatus, layout verification method, layout verification program, and wiring forming method
摘要 The layout verification apparatus includes: a verification unit for obtaining mask data indicating a mask pattern to be drawn on a mask based on layout and wiring data indicating positions of a group of primitive cells and positions of connection wires connected to the group of primitive cells, and for verifying a position of the mask pattern based on the mask data, so as to detect an error part; and a correction hint creating unit for creating correction hint information based on the error part, and for sending the correction hint information to a layout and wiring unit for correcting the layout and wiring data. The correction hint creating unit obtains terminal information indicating positions of a group of terminals included in the group of primitive cells and creates the correction hint information based on the terminal information so that the positions of the group of terminals are not changed by the layout and wiring unit.
申请公布号 US2010115765(A1) 申请公布日期 2010.05.13
申请号 US20090585441 申请日期 2009.09.15
申请人 NEC ELECTRONICS CORPORATION 发明人 HAMAMOTO TAKESHI
分类号 H01R43/00;G06F17/50 主分类号 H01R43/00
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