发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUITS WITH POWER REDUCTION MECHANISM |
摘要 |
A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.
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申请公布号 |
US2010109702(A1) |
申请公布日期 |
2010.05.06 |
申请号 |
US20090645784 |
申请日期 |
2009.12.23 |
申请人 |
SAKATA TAKESHI;ITOH KIYOO;HORIGUCHI MASASHI |
发明人 |
SAKATA TAKESHI;ITOH KIYOO;HORIGUCHI MASASHI |
分类号 |
H03K19/003;G05F1/10;G11C5/14;G11C7/06;G11C8/08;G11C8/12;H03K19/00 |
主分类号 |
H03K19/003 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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