| 摘要 |
<P>PROBLEM TO BE SOLVED: To avoid an increase in resistance of a gate electrode and wiring while attaining high integration by preventing disconnection of a metal silicide film due to approach of a hole to a PN junction boundary in a structure having the PN junction boundary and the hole formed on the gate electrode and the wiring with the metal silicide film formed on the surface. Ž<P>SOLUTION: An N-type polycrystalline silicon region 103A and a P-type polycrystalline silicon region 103B are formed in a polycrystalline silicon film 103 as the gate electrode to be adjacent to each other with the PN junction boundary 105 interposed. The metal silicide film 104 is formed on the polycrystalline silicon film 103 across the PN junction boundary 105. The PN junction boundary 105 is disposed not to constitute a vertical plane relative to a direction in which the gate electrode extends. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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