| 摘要 |
PURPOSE: A layout of a semiconductor device is provided to prevent defects due to electrical short between a dummy gate line and a bit line contact by changing a layout of a dummy gate line so that the voltage level of the dummy gate line and the voltage level of the bit line are identically sensed. CONSTITUTION: A dummy gate line(22) is included in the edge section of the cell mat. A segment mouth/output line(23) is included in the sense amplifier region which is contiguous to the cell mat. It is expanded in the top or the lower part of the cell mat and the dummy gate line is connected to the segment mouth/output line. The segment mouth/output line a plurality of lines having one or more pairs.
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