发明名称 Synchronization system using redundant clock signals for equipment of a synchronous transport network
摘要 A synchronization system (D) for equipment of a synchronous transport network comprises, firstly, a first synchronization module (MA) comprising i) a first submodule (SM1A) delivering a first intermediate clock signal derived from a first external reference clock signal or an internal reference clock signal, ii) a second submodule (SM2A) delivering a first main reference clock signal derived from the first intermediate clock signal or a second intermediate clock signal, and iii) a third submodule (SM3A) delivering a first output reference clock signal derived from the first main reference clock signal or a second main reference clock signal, and, secondly, a second synchronization module (MB) comprising i) a first submodule (SM1B) delivering the second intermediate clock signal derived from another first external reference clock signal and another internal reference clock signal, ii) a second submodule (SM2B) delivering the second main reference clock signal derived from the first or the second intermediate clock signal, and iii) a third submodule (SM3B) delivering a second output reference clock signal derived from the first or the second main reference clock signal.
申请公布号 US7706413(B2) 申请公布日期 2010.04.27
申请号 US20050090596 申请日期 2005.03.28
申请人 ALCATEL 发明人 DOLLO PHILIPPE;STEPHAN YANNICK;MORIN BENOIT
分类号 H04J3/06 主分类号 H04J3/06
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