| 摘要 |
PROBLEM TO BE SOLVED: To allow access to all memory cells of a memory module, and to normally operate the memory module, even when the numbers of bits of a column address, a row address, and a bank address output from a memory controller do not match the numbers of bits of a column address, a row address, and a bank address for specifying a memory cell that is an access target, in the memory module. SOLUTION: In this memory module 100, an address generation circuit 120 generates the highest order bit B2 of the bank address insufficient for the purpose of specification of the memory cell that is the access target by use of the highest order bit of the row address output from the memory controller 12, and outputs it to SDRAM (Synchronous Dynamic Random Access Memory) 110. An operation mode detection unit 130 detects an operation mode of the memory controller 12. A switch control unit 140 switches a switch 128, based on the detected operation mode. COPYRIGHT: (C)2010,JPO&INPIT |
