| 摘要 |
connecting a gate common junction point of P-MOS transistors (P1,P2) and N-MOS tr. N1 at a ground unit (VSS), connecting VCC to the source of the P-MOS tr. P1 connected to a source common junction point of a P-MOS transistors P2, P3, connecting the source common junction point to the drain of the N-MOS tr. N1 and connecting the source of the N-MOS tr. N1 to VBB sequentially through N-MOS transistors N2,N3,N4 which are connected the gate and the drain , connecting a drain common junction point of the P-MOS transistors P2,P3 and the N-MOS tr. N1 to an one side input unit of NAND1, connecting an output unit of NAND1 to the gate of the P-MOS tr. P3 and to an input unit of an inverter INV1, connecting an output unit of the inverter INV1 to an one side input of NAND2 in which a PWRUP is connected to an other input unit through INV2, simultaneously connecting it to an one side input unit of NOR which a GENPULSE is connected to an other side input unit, connecting an output unit of NAND2 to a OSCEW through INV3, connecting an output unit of NOR to the other side input unit of NAND1 through INV4, and connecting it to of a voltage level shifter section 10 an input unit for controlling ON/OFF of the N-MOS tr. N4.
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