| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a microcomputer properly receiving a break instruction issued by an ICE (In Circuit Emulator) even when a CPU executes a periodic task and a non-periodic task in parallel. Ž<P>SOLUTION: The CPU 2 has: a task changeover register 7 storing a return address when changing over between the periodic task and the non-periodic task; and a break register 11 storing a return address when the break instruction is issued by the ICE 14. When a simultaneous occurrence detection part 13 detects that the issuance of the break instruction and the changeover between the periodic task and the non-periodic task by the CPU 2 have simultaneously occurred, an address processing part 18 of a monitor program 17 replaces the address stored in the task changeover register 7 and the address stored in the break register 11. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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