摘要 |
<p>A data processing system (10) has an interrupt controller (14) which provides an interrupt request (30) along with a corresponding interrupt identifier (31) and a corresponding interrupt vector (32) to a processor (20). If the processor (20) accepts the interrupt, the processor (20) returns the same interrupt identifier (31) value by way of interrupt identifier (34), along with interrupt acknowledge (33), to the interrupt controller (14). An interrupt taken/not taken indicator (35) may also be provided. The communications interface (60, 40, 70) used to coordinate interrupt processing between the interrupt controller (14) and the processor (20) may be asynchronous.</p> |
申请人 |
FREESCALE SEMICONDUCTOR INC.;MARIETTA, BRYAN, D.;SNYDER, MICHAEL, D.;WHISENHUNT, GARY, L.;BOUVIER, DANIEL, L. |
发明人 |
MARIETTA, BRYAN, D.;SNYDER, MICHAEL, D.;WHISENHUNT, GARY, L.;BOUVIER, DANIEL, L. |