| 摘要 |
An equalizer includes a tapped delay line and an adder. The tapped delay line includes a plurality of taps cascaded to each other. The tapped delay line receives an input signal, a plurality of tap control signals, and a plurality of tap coefficients and generates a plurality of multiplied signals. The plurality of taps is divided into a plurality of groups. The adder is coupled to the tapped delay line for adding the plurality of multiplied signals up to generate an output signal.
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