| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a shift register circuit capable of preventing the level change speed of an output signal from degrading, reducing power consumption, and preventing malfunction caused by noise applied to an output terminal. <P>SOLUTION: An unit shift register includes a transistor Q1 supplying a clock signal CLK to an output terminal OUT, a transistor Q2 discharging the output terminal OUT, a transistor Q3 charging a gate of the transistor Q1, and a transistor Q4 discharging the gate of the transistor Q1. Further, the unit shift register includes a drive circuit which supplies a signal in which an output signal G<SB>k</SB>output from the output terminal OUT is reversed to gates of the transistors Q2, Q4, and which has hysteresis characteristics. <P>COPYRIGHT: (C)2010,JPO&INPIT |
