发明名称 VERFAHREN UND GERÄT ZUM BEWIRKEN EINER VERBINDUNG VON VARIABLER BREITE
摘要 Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.
申请公布号 AT464607(T) 申请公布日期 2010.04.15
申请号 AT20040257160T 申请日期 2004.11.18
申请人 INTEL CORPORATION 发明人 STEINMAN, MAURICE B.;CHERUKURI, NAVEEN;SPINK, AARON T.;BAUM, ALLEN J.;DABRAL, SANJAY;FRODSHAM, TIM;SHAH, RAHUL R.;DUNNING, DAVIS S.;SCHOENBORN, THEODORE Z.
分类号 G06F13/38;G06F13/40;H04L12/26;H04L12/28;H04L29/08 主分类号 G06F13/38
代理机构 代理人
主权项
地址