| 摘要 |
A method and system for improving reliability of OTP memories, and in particular anti-fuse memories, by storing one bit of data in at least two OTP memory cells. Therefore each bit of data is read out by accessing the at least two OTP memory cells at the same time in a multi-cell per bit mode. By storing one bit of data in at least two OTP memory cells, defective cells or weakly programmable cells are compensated for since the additional cell or cells provide inherent redundancy. Program reliability is ensured by programming the data one bit at a time, and verifying all programmed bits in a single-ended read mode, prior to normal operation where the data is read out in the multi-cell per bit mode. Programming and verification is achieved at high speed and with minimal power consumption using a novel program/verify algorithm for anti-fuse memory. In addition to improved reliability, read margin and read speed are improved over single cell per bit memories.
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