发明名称 |
Test circuit for measuring resistance distribution of Memory cells and semiconductor system including the same |
摘要 |
The test circuit for measuring a resistance distribution of memory cells includes a sensing circuit and a digital value generation circuit. The sensing circuit compares a reference voltage with a voltage of a sensing node receiving a voltage of a bit line connected with a resistive element and generates a sensing signal. The digital value generation circuit generates a digital value corresponding to a resistance-capacitance (RC) delay of the bit line in response to the sensing signal from the sensing circuit.
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申请公布号 |
US2010085826(A1) |
申请公布日期 |
2010.04.08 |
申请号 |
US20090588192 |
申请日期 |
2009.10.07 |
申请人 |
KANG SANG BEOM;KIM HO JUNG |
发明人 |
KANG SANG BEOM;KIM HO JUNG |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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