| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a method for designing a semiconductor integrated circuit capable of reducing power consumption in a functional macro test by providing a control circuit for a gated clock buffer (GCB). Ž<P>SOLUTION: In the method, a function-described specification of a semiconductor integrated circuit is logically composed, and a GCB which requires the propagation of a clock in a memory test is then extracted from a net list 1 (S1-1). From all GCBs on a chip except the GCB extracted in a step S1-1, a GCB which requires no propagation of the clock in the memory test is extracted (S1-2). The addition of a control circuit for laying the GCB requiring the propagation of the clock in the memory test which is extracted in the step S1-1 into a clock propagating state in the memory test and in a logic test to the net list 1 and the addition of a control circuit for laying the GCB requiring no propagation of the clock in the memory test which is extracted in a step S1-2 to the net list 1 are performed (S1-3). Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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