发明名称
摘要 A semiconductor memory has a memory unit including a regular cell array having a plurality of memory cells and a decoder for decoding an input address and selecting a memory cell corresponding to the input address in the regular cell array, in which an access operation is performed to the selected memory cell; a defective address storage section which stores a defective address corresponding to a defective bit in the regular cell array; and a replacement address storage section which stores a replacement address corresponding to a replacement bit in the regular cell array. When a supply address supplied to the memory unit matches the defective address, the replacement address, in place of the supply address, is supplied to the memory unit as the input address, according to which the access operation is performed.
申请公布号 JP4447533(B2) 申请公布日期 2010.04.07
申请号 JP20050232841 申请日期 2005.08.11
申请人 发明人
分类号 G11C29/04;G11C11/401;G11C29/12;G11C29/44 主分类号 G11C29/04
代理机构 代理人
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