发明名称 INFORMATION PROCESSING APPARATUS
摘要 <P>PROBLEM TO BE SOLVED: To suppress a redundant circuit configuration when detecting a failure of a decoder. Ž<P>SOLUTION: An information processing apparatus contains a memory section (20) having a plurality of word lines, and a decoder (30) for forming a selection signal to select the word lines by decoding an address signal, and the decoder contains a first selector circuit (11), a first decoder circuit (12_0), a second decoder circuit (12_1), and a comparator circuit (13). The comparator forms a failure signal for enabling failure determination of a decoding function of the decoder by comparing a pair of bit signals asserted by the decoder circuit. According to the configuration, a plurality of the same configuration circuits of the decoder and memory section are mounted for examining conformance and nonconformance of the result, resulting in significant reduction of the redundancy of the decoder comparing with technology for detecting a malfunction. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010073285(A) 申请公布日期 2010.04.02
申请号 JP20080242236 申请日期 2008.09.22
申请人 RENESAS TECHNOLOGY CORP 发明人 MIYAKOSHI JUNICHI;KATO NAOKI;YAMADA TETSUYA
分类号 G11C29/12 主分类号 G11C29/12
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