发明名称 METHOD FOR FABRICATING INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DEVICES
摘要 Described herein are methods for fabricating dual-damascene interconnect structures. In one embodiment, the interconnect structures are fabricated with a dual-damascene method having trenches then vias formed. The method includes novel liner depositions after the trench and via etches. The method includes etching trenches in a dielectric layer. Next, the method includes depositing a first liner layer on the dielectric layer. Next, the method includes etching vias in the dielectric layer and an etch stop layer. Next, the method includes depositing a second liner layer on the first liner layer. The second liner layer is deposited on the exposed surfaces of the first liner layer, dielectric layer, etch stop layer, and the first metal layer. Then, a second metal layer is deposited on the second liner layer.
申请公布号 US2010078825(A1) 申请公布日期 2010.04.01
申请号 US20080240061 申请日期 2008.09.29
申请人 PATZ RYAN JAMES;PEIDOUS IGOR;PENDER JEREMIAH;ARMACOST MICHAEL D 发明人 PATZ RYAN JAMES;PEIDOUS IGOR;PENDER JEREMIAH;ARMACOST MICHAEL D.
分类号 H01L23/48;H01L21/4763 主分类号 H01L23/48
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