发明名称 Silicon-alloy based barrier layers for integrated circuit metal interconnects
摘要 A method for forming a silicon alloy based barrier layer comprises providing a substrate having a dielectric layer including a trench, placing the substrate in a reactor, and carrying out a process cycle, wherein the process cycle comprises introducing a silicon containing precursor into the reactor, introducing a metal containing precursor into the reactor, and introducing a co-reactant into the reactor, wherein the silicon, metal, and co-reactant react to form a silicon alloy layer that is conformally deposited on a bottom and a sidewall of the trench.
申请公布号 US7687911(B2) 申请公布日期 2010.03.30
申请号 US20060517736 申请日期 2006.09.07
申请人 INTEL CORPORATION 发明人 DOMINGUEZ JUAN E.;LAVOIE ADRIEN R.
分类号 H01L21/48 主分类号 H01L21/48
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